1. Field of the Invention
The present invention generally relates to methods and apparatus for electropolishing metal layers on semiconductor wafers. More particularly, the present invention relates to a system for electropolishing interconnections in semiconductor devices formed on semiconductor wafers.
2. Description of the Related Art
In general, semiconductor devices are manufactured or fabricated on disks of semiconducting materials called wafers or slices. More particularly, wafers are initially sliced from a silicon ingot. The wafers then undergo multiple masking, etching, and deposition processes to form the electronic circuitry of semiconductor devices.
During the past decades, the semiconductor industry has increased the power of semiconductor devices in accordance with Moore's law, which predicts that the power of semiconductor devices will double every 18 months. This increase in the power of semiconductor devices has been achieved in part by decreasing the feature size (i.e., the smallest dimension present on a device) of these semiconductor devices. In fact, the feature size of semiconductor devices has quickly gone from 0.35 microns to 0.25 microns, and now to 0.18 microns. Undoubtedly, this trend toward smaller semiconductor devices is likely to proceed well beyond the sub-0.18 micron stage.
However, one potential limiting factor to developing more powerful semiconductor devices is the increasing signal delays at the interconnections (the lines of conductors, which connect elements of a single semiconductor device and/or connect any number of semiconductor devices together). As the feature size of semiconductor devices has decreased, the density of interconnections on the devices has increased. However, the closer proximity of interconnections increases the line-to-line capacitance of the interconnections, which results in greater signal delay at the interconnections. In general, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays (i.e., delay at the gates or mesas of semiconductor devices) have been found to increase linearly with the reduction in feature size.
One conventional approach to compensate for this increase in interconnection delay has been to add more layers of metal. However, this approach has the disadvantage of increasing production costs associated with forming the additional layers of metal. Furthermore, these additional layers of metal generate additional heat, which can be adverse to both chip performance and reliability.
Consequently, the semiconductor industry has started to use copper rather than aluminum to form the metal interconnections. One advantage of copper is that it has greater conductivity than aluminum. Also, copper is less resistant to electromigration (meaning that a line formed from copper will have less tendency to thin under current load) than aluminum. However, one significant disadvantage to using copper has been its tendency to bleed into the silicon substrate, thus contaminating the semiconductor device.
Additionally, before copper can be widely used for interconnections, new processing techniques are required. More particularly, in a conventional damascene process, metal is patterned within canal-like trenches and/or vias. The deposited metal is then polished back using chemical mechanical polishing (“CMP”). In general, depending on the interconnection structure design, anywhere from half a micron to 1.5 millimeters of metal needs to be polished. Polishing such a large quantity of metal using conventional CMP requires a long polishing time and consumes a large quantity of slurry, which leads to high manufacturing costs.